Process for etching and depositing integrated circuit interconnections and contacts
US5354711A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1993 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Jul 8, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for producing an integrated circuit stage formed from a dielectric layer (1) covering interconnection lines (5) and connection points (4), which connect the said lines (5) to conductive parts (6) on the opposite side of the dielectric layer (1). The process consists of forming all the dielectric layer (1) during a single step and then successively etching cavities at the locations of the connection points and the interconnection lines by means of two successively positioned masks and then filling the cavities in a single step with conductive material in order to simultaneously form connection points (4) and interconnection lines (5).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.