High speed bus system
US5355391A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1992 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Mar 6, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In the high speed bus system of the present invention, the bus configuration is one in which all master devices are clustered at one end of an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is terminated. By eliminating the termination resistor at the end of the bus where the master devices are located the required drive current needed to produce a given output swing is reduced. The bus drivers and receivers are CMOS integrated circuits. The bus of the present invention is operable utilizing small swing signals which enable sufficient implementation of current mode drivers for low impedance bus signals. In particular, the bus input receiver of the present invention comprises a two stage buffered sampler/amplifier which receives a small swing signal from the bus and samples and amplifies the low swing signal to a full swing signal within a single clock cycle using CMOS circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.