Winston Lee
92Patents
18h-index
34Co-inventors
84Inventor score
Filing activity: Apr 16, 1987 → Sep 16, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5172338A | Multi-state EEprom read and write circuits and techniques | Physics | 1,216 | Expired |
| US5163021A | Multi-state EEprom read and write circuits and techniques | Physics | 442 | Expired |
| US6754746B1 | Memory array with read/write methods | Emerging Cross-Sectional Technologies | 435 | Expired |
| US5432823A | Method and circuitry for minimizing clock-data skew in a bus system | Electricity | 389 | Expired |
| US5355391A | High speed bus system | Emerging Cross-Sectional Technologies | 353 | Expired |
| US5428621A | Latent defect handling in EEPROM devices | Physics | 240 | Expired |
| US5655113A | Resynchronization circuit for a memory system and method of operating same | Emerging Cross-Sectional Technologies | 219 | Expired |
| US5498990A | Reduced CMOS-swing clamping circuit for bus lines | Emerging Cross-Sectional Technologies | 141 | Expired |
| US6393504B1 | Dynamic address mapping and redundancy in a modular memory device | Emerging Cross-Sectional Technologies | 79 | Expired |
| US4797856A | Self-limiting erase scheme for EEPROM | Physics | 53 | Expired |
| US5729152A | Termination circuits for reduced swing signal lines and methods for operating same | Emerging Cross-Sectional Technologies | 50 | Expired |
| US5659550A | Latent defect handling in EEPROM devices | Physics | 39 | Expired |
| US7734966B1 | Method and system for memory testing and test data reporting during memory testing | Physics | 24 | Active |
| US7571287B2 | Multiport memory architecture, devices and systems including the same, and methods of using the same | Physics | 21 | Active |
| US6272577A | Data processing system with master and slave devices and asymmetric signal swing bus | Emerging Cross-Sectional Technologies | 20 | Expired |
| US7609538B1 | Logic process DRAM | Electricity | 20 | Active |
| US5737587A | Resynchronization circuit for circuit module architecture | Emerging Cross-Sectional Technologies | 20 | Expired |
| US8335878B2 | Multiport memory architecture, devices and systems including the same, and methods of using the same | Physics | 19 | Active |
| US8030128B1 | Method to form high density phase change memory (PCM) top contact every two bits | Electricity | 15 | Active |
| US6570781B1 | Logic process DRAM | Electricity | 12 | Expired |
| US8004926B2 | System and method for memory array decoding | Physics | 11 | Active |
| US9652246B1 | Banked physical register data flow architecture in out-of-order processors | Physics | 10 | Active |
| US8911275B2 | Building elements with sonic actuation | Human Necessities | 10 | Active |
| US8605534B2 | Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes | Physics | 10 | Active |
| US7184290B1 | Logic process DRAM | Electricity | 9 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.