MOS transistor with an integrated protection zener diode
US5357126A · kind A · utility
10Cited by
3References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 19, 1992 |
| Grant date | Oct 18, 1994 |
| Priority date | — |
| Expiry date | Nov 19, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A MOS transistor is formed in a first low-doped P-type retion coating a second more highly doped P-type region. The transistor comprises an N-type drain region, an N-type source region, and a region contacting the for region. The drain, cource and contacting regions are formed at the surface of the first region. The source and contacting regions are interconnected. An N-type highly doped region extends from the drain region through the first low-doped P-type region to the second more highly doped P-type region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.