Macrocell with product-term cascade and improved flip flop utilization

US5357153A · kind A · utility

Assignee

• XILINX, INC. · US

Inventors

• David Chiang · Saratoga, US
• Napoleon W. Lee · Milpitas, US
• Thomas Y. Ho · Milpitas, US
• David Harrison · San Francisco, US
• Nicholas Kucharewski · Lebanon, US
• Jeffrey H. Seltzer · San Jose, US

Key dates

• Filing date: Jan 28, 1993
• Grant date: Oct 18, 1994
• Expiry date: Jan 28, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17704
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.