System for allowing a content addressable memory to operate with multiple power voltage levels
US5357458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1993 |
| Grant date | Oct 18, 1994 |
| Priority date | — |
| Expiry date | Jun 25, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/789
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for allowing a content addressable memory (CAM) to operate with first and second power voltage levels including: a first input voltage for providing a first bias to the content addressable memory; a second input voltage for providing a second bias to the content addressable memory; and a selection device coupled to the first input voltage and the second input voltage for decoupling the first input voltage from the content addressable memory and coupling the second input voltage to the content addressable memory in response to coupling the second power voltage level to the content addressable memory. In a specific embodiment the system includes: a first power on reset coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and a second power on reset coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the content addressable memory. The system allows a CAM to operate at a power voltage level of 2.6 to 3.6 volts to reduce power dissipation and at a higher …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.