Method of making gate overlapped lightly doped drain for buried channel devices
US5358879A · kind A · utility
89Cited by
11References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/114
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process to form poly sidegate LDD structures on buried channel MOSFETs is described. A polysilicon spacer is formed on the gate after source/drain processing. The spacer is later shorted to the main gate by implantation of neutral impurities. The process is particularly suited for SOI technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.