Method for planarization of submicron vias and the manufacture of semiconductor integrated circuits
US5360524A · kind A · utility
Inventors
Key dates
| Filing date | Apr 13, 1993 |
| Grant date | Nov 1, 1994 |
| Priority date | — |
| Expiry date | Apr 13, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Submicron vias are filled by sputter deposition of a conductor such as aluminum onto a substrate such as silicon or silicon oxides. The deposited aluminum film is deposited at a first lower temperature and then the temperature is increased. The differential coefficient of thermal expansion of the substrate relative to the metal conductor forces the conductor to expand into the via. Maintaining an effective thickness and controlling the temperature increase from the first temperature to the second temperature, effectively and reliably fills submicron vias having aspect ratios up to 4. The present invention is particularly useful with filling vias having re-entrant angles of up to 20.degree..
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.