Integrated semiconductor device having a buried semiconductor layer and fabrication method thereof
US5362981A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1993 |
| Grant date | Nov 8, 1994 |
| Priority date | — |
| Expiry date | Jan 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A structure and its fabrication method of an integrated semiconductor device including circuit elements such as MOSFETs. A well is formed in the semiconductor substrate within windows of a field oxide layer. A lightly-doped semiconductor layer is selectively formed on the exposed surface of the well. A channel region and a pair of source and drain regions of a MOSFET are formed in the lightly-doped semiconductor layer. The highly-doped buried semiconductor layer of the same conductivity type as that of the lightly-doped semiconductor layer is formed under the channel region in the lightly-doped semiconductor layer. The structural features and fabrication method provides a great degree of freedom in designing a MOSFET having a further shorter-channel length without deteriorating its drivability and punch-through breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.