Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming
US5363330A · kind A · utility
70Cited by
5References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 28, 1991 |
| Grant date | Nov 8, 1994 |
| Priority date | — |
| Expiry date | Jan 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.