Germanium implanted stacked capacitor cell

US5364814A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Mark McQueen · Boise, US

Key dates

• Filing date: Oct 6, 1993
• Grant date: Nov 15, 1994
• Expiry date: Oct 6, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/31

Abstract

A method of fabricating a stacked capacitor memory cell having a reduced leakage storage node includes the steps of providing a P-type substrate, forming wordlines on a thin gate oxide layer and a field oxide layer, and forming a first conformal TEOS oxide layer. The P-type substrate is doped with an N-type dopant directly through the first TEOS oxide layer to form two N-type diffused areas, which are the first and second current terminals of the memory cell access transistor. A second conformal TEOS oxide layer is deposited. The oxide layers are etched to form a buried contact window above the storage node of the memory cell. The exposed portion of the N-type diffused area forming the memory cell storage node is subsequently doped with germanium through the buried contact window to suppress any outdiffusion due to the doping of subsequently formed layers, such as the first plate of a stacked polysilicon capacitor. The first plate of the stacked capacitor is formed above the buried contact window, and is in contact with the germanium and N-type dopant diffused area. Although the first plate of the stacked capacitor is heavily doped, outdiffusion is limited by the action of the germ…