Method of manufacturing an integrated circuit including planarizing a wafer
US5366924A · kind A · utility
10Cited by
13References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1992 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Mar 16, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for planarizing a bonded wafer. The wafer has a layer of exposed oxide thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer for subsequent fabrication of transistors, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.