Vertical JFET transistor with optimized bipolar operating mode and corresponding method of fabrication
US5367184A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1993 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Jul 2, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/831
Abstract
The vertical junction field-effect transistor comprises a semiconductor structure including an internal semiconductor layer (23, 26) extending within the channel region (7) between the gate region (4, 31), this internal layer being produced in a semiconductor material, having an energy gap (Eg.sup.2) smaller than that of the material forming the channel and gate regions, and the same type of conductivity (N) as that of the channel region, and the heterojunction formed between this internal layer and the channel region exhibits a band discontinuity situated in the valence band in the case of a N-type channel, or in the conduction band in the case of a P-type channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.