Output buffer circuit for a low voltage EPROM
US5367206A · kind A · utility
4Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1993 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Jun 17, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit is disclosed that operates in low voltage applications but can be programmed using standard programmers at high voltage. The output buffer circuit provides for detecting a program verify logic signal from the programmer and slowing the output driver transistors when that signal is detected. In so doing, the noise problems associated with the higher voltages of programming a EPROM device are eliminated while at the same time allowing the output buffer circuit to operate at the required performance levels during normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.