DRAM having bidirectional global bit lines
US5367488A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 1993 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Mar 18, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM having bidirectional global bit lines is defined such that local bit lines connected to corresponding memory cells and separative global bit lines connected to the local bit lines are commonly connected to local bit lines so as to read data stored in the cells or write data to the cells in a bidirectional data access manner. According to the DRAM of the present invention, the sense amplifiers, input and output lines and switching elements for column decoding, which generally are located between adjacent cell arrays, can be advantageously positioned without decreasing the characteristics of the DRAM element. In addition, the DRAM of the present invention employs an open bit line structure rather than a folded bit line structure, thereby improving a packing effect as well as a S/N (signal-to-noise) characteristic, remarkably.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.