Randomly accessible memory having time overlapping memory accesses
US5367494A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1993 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Aug 31, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.