Digital data recovery using delay time rulers
US5367542A · kind A · utility
40Cited by
3References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 19, 1992 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Jun 19, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
All digital, high frequency data separation receiver apparatus and method for ascertaining the correct sequence of received digital data without a phase locked loop or an analogue voltage control oscillator (VCO) method, which employs a series of time delay circuits to establish time rulers to unambiguously determine the sequence of received bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.