Memory with isolated digit lines
US5369622A · kind A · utility
147Cited by
6References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 20, 1993 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Apr 20, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory in which a portion of a digit line is isolated from the remainder of the digit line during a write cycle has improved performance. In the conventional architecture of a memory device, cells are arranged in rows and columns and a sense amplifier is employed for a pair of columns, located between a pair of complementary digit lines. An embodiment of the present invention in this architecture provides improved means for isolating the sense amplifier during a write cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.