Method to solve sog non-uniformity in the VLSI process
US5371046A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Jul 22, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02282
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of planarizing an integrated circuit is described. A first coating of a silicate spin-on-glass material is applied to the surface of a patterned conductor layer to be planarized. The spin-on-glass material is applied under low relative humidity, filling the valleys of the irregular structure of the conductor layer. The first spin-on-glass layer is covered with a second coating of the spin-on-glass material also applied under low relative humidity. Then, both first and second spin-on-glass layers are cured. This method provides a uniform spin-on-glass dielectric layer upon which a second conductor layer may now be successfully applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.