Non-volatile ferroelectric memory with folded bit lines and method of making the same
US5371699A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1992 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Nov 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile ferroelectric memory having folded bit lines both reduces the size of the memory while also eliminating noise interference commonly associated with non-volatile ferroelectric memories having an open bit line architecture. The memory provides two pairs of coincident word and plate lines associated with each row, viz., plate line A paired with word line B, and plate line B paired with word line A. The plate line of a pair may overlie or underlie the word line of the pair, and one may have the same width or a different width as the other of the pair, but preferably the elements of the pair are generally aligned, and the elements of the other pair are aligned with themselves, the two pairs being distally spaced apart. Each cell in the row is connected at the appropriate location to a word line of one of the pairs and a plate line of the other pair. Therefore, the word line and plate line of any single cell are not coincident. Further, adjacent cells in any row do not share the same word line or plate line, but are connected to the other word line or plate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.