William Larson
25Patents
11h-index
15Co-inventors
72Inventor score
Filing activity: Jun 20, 1989 → May 11, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5005102A | Multilayer electrodes for integrated circuit capacitors | Emerging Cross-Sectional Technologies | 151 | Expired |
| US5206788A | Series ferroelectric capacitor structure for monolithic integrated circuits and method | Emerging Cross-Sectional Technologies | 88 | Expired |
| US5216572A | Structure and method for increasing the dielectric constant of integrated ferroelectric capacitors | Emerging Cross-Sectional Technologies | 72 | Expired |
| US5580814A | Method for making a ferroelectric memory cell with a ferroelectric capacitor overlying a memory transistor | Electricity | 61 | Expired |
| US5495117A | Stacked ferroelectric memory cell | Electricity | 45 | Expired |
| US6424561B1 | MRAM architecture using offset bits for increased write selectivity | Electricity | 40 | Expired |
| US6392922B1 | Passivated magneto-resistive bit structure and passivation method therefor | Electricity | 31 | Expired |
| US5371699A | Non-volatile ferroelectric memory with folded bit lines and method of making the same | Physics | 30 | Expired |
| US6806546B2 | Passivated magneto-resistive bit structure | Electricity | 29 | Expired |
| US5907784A | Method of making multi-layer gate structure with different stoichiometry silicide layers | Electricity | 18 | Expired |
| US5635765A | Multi-layer gate structure | Electricity | 17 | Expired |
| US6717194B2 | Magneto-resistive bit structure and method of manufacture therefor | Electricity | 9 | Expired |
| US6522574B2 | MRAM architectures for increased write selectivity | Electricity | 7 | Expired |
| US6424564B1 | MRAM architectures for increased write selectivity | Electricity | 6 | Expired |
| US6872997B2 | Method for manufacture of magneto-resistive bit structure | Electricity | 4 | Expired |
| US6623987B2 | Passivated magneto-resistive bit structure and passivation method therefor | Electricity | 4 | Expired |
| US7169679B2 | Varactor with improved tuning range | Electricity | 3 | Expired |
| US6791856B2 | Methods of increasing write selectivity in an MRAM | Electricity | 2 | Expired |
| US7029923B2 | Method for manufacture of magneto-resistive bit structure | Electricity | 2 | Expired |
| US9818742B2 | Semiconductor device isolation using an aligned diffusion and polysilicon field plate | Electricity | 1 | Active |
| US5821623A | Multi-layer gate structure | Electricity | 1 | Expired |
| US6992918B2 | Methods of increasing write selectivity in an MRAM | Electricity | 1 | Expired |
| US6756240B2 | Methods of increasing write selectivity in an MRAM | Electricity | 0 | Expired |
| US7427514B2 | Passivated magneto-resistive bit structure and passivation method therefor | Electricity | 0 | Expired |
| US8536659B2 | Semiconductor device with integrated channel stop and body contact | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.