Semiconductor memory device having detection circuitry for sensing faults in word lines
US5371712A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Mar 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device facilitated with a test circuit having a simple construction of a plurality of MOSFETs having their individual gates connected with a plurality of word lines in a memory array; and a testing pad for detecting the presence of an electric current flowing between the sources and drains of the plurality of MOSFETs. If the word line is short-circuited to the power supply to achieve an intermediate potential equal to or higher than the threshold voltage of the MOSFETs, an electric current will flow through the MOSFETs so that the presence of the short-circuit between the word lines and the power supply can be accurately detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.