Method and apparatus for providing an uninterrupted clock signal in a data processing system
US5371764A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1992 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Jun 26, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital computer is provided having a clock generation circuit for generating a clock signal in response to an input signal from a fixed-frequency oscillator, which includes a first fixed-frequency oscillator and a second fixed-frequency oscillator, each providing an output signal. Also included is failure detection circuit for detecting a failure of either of the fixed-frequency oscillators, wherein a failure occurs when the first fixed-frequency oscillator or the second fixed-frequency oscillator ceases generating an output. A circuit synchronizing the output from the oscillators is coupled to both the first fixed-frequency oscillator and to the second fixed-frequency oscillator. This synchronizing circuit modifies the output from the second fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with the output from the first fixed frequency oscillator. A switching circuit is coupled to the failure detection circuit, the output from the first fixed-frequency oscillator and the synchronized output of the second fixed-frequently oscillator. The switching circuit normally couples the output of the first fixed-frequency oscillator as the clock…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.