Bus synchronization apparatus and method
US5371880A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 1992 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | May 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Several techniques are used to optimize the transmission of signals or events from one bus to the other. In one aspect, the user of a chipset is permitted to choose whether the originating events (i.e. the events in response to which a destination event is to be generated on a destination bus) are to be generated synchronously or asynchronously with the clock signal on the destination bus. Whether synchronous or asynchronous generation is chosen, the chipset may perform a synchronization function in response to an originating bus predictor signal. The number of destination clock cycles to delay before generating the desired destination bus event is responsive to the relative frequencies of the clock signals on the two buses, thereby accommodating a wide variety of such relative frequencies. In another aspect, for events to be generated on a destination bus synchronously with a clock signal which is by specification stretchable, the destination bus event is generated promptly in response to the originating event and then the destination bus clock signal is stretched to make the destination bus event synchronous with the destination bus clock signal. The length of the stretch is resp…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.