Planarized local oxidation by trench-around technology
US5372968A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1993 |
| Grant date | Dec 13, 1994 |
| Priority date | — |
| Expiry date | Sep 27, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of local oxidation using trench-around technology is described. A first silicon oxide layer is deposited over the surface of a silicon substrate. A plurality of wide and narrow openings are etched through portions of the first silicon oxide layer not covered by a mask pattern to the silicon substrate. A layer of silicon nitride is patterned to form a set of spacers on the sidewalls of the patterned first silicon oxide layer which will fill the narrow openings. The first silicon oxide layer is partially etched away whereby the substrate within the central portions of the wide openings will be etched to form shallow trenches. The patterned first silicon oxide layer and the silicon nitride spacers are covered with spin-on-glass material which is baked and cured, then etched back leaving the spin-on-glass material only within the wide openings within the shallow trenches. The silicon nitride spacers are removed and deep trenches are etched into the silicon substrate under the spacers whereby the deep trenches are formed at the location of the narrow openings and at the outside edges of the wide openings flanking the shallow trenches. The deep trenches are filled with a second …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.