Laminated substrate for semiconductor device and manufacturing method thereof
US5374582A · kind A · utility
13Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1994 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Apr 28, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/012
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a laminated substrate for a semiconductor device having a high voltage power device and a low voltage element formed in a region isolated from the power device with a P-N junction. The region for the low voltage element is formed on a buried layer of P type formed in the region of N type in which the power device is formed and surrounded by a isolating region of P type reaching the buried layer from the surface of the laminated substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.