Plural port memory system utilizing a memory having a read port and a write port
US5375089A · kind A · utility
113Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 5, 1993 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Oct 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plural port memory system utilizing a memory having a write port and a separate read port wherein the write port includes a write data line, a write address, and a write enable line and wherein the read port includes a read data line, a read address, and a read enable line. The plural port memory system includes: a plurality of interfaces for reading from and writing to the memory, each interface having a read request line and a write request line; and a controller coupled to each of the read and write request lines, and the read and write enable lines for arbitrating access to the memory by the plurality of interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.