Method and apparatus for memory dynamic burn-in and test
US5375091A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1993 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Dec 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.