Temperature detecting circuit and dynamic random access memory device
US5375093A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1993 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Jan 21, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Delay circuit 11 is composed of eight-stage NOT circuits. Polysilicon resistors RPS11 and RPS12 are connected to the sources of P channel type MOS transistor Qp12 and N channel type MOS transistor Qn12 in the second stage NOT circuit. These polysilicon resistors exhibit a smaller temperature dependency, as shown by dot lines in FIG. 2. The delay time of the eight-stage NOT circuits as a whole shows a smaller temperature dependency. Delay circuit 12 in FIG. 1 is composed of three-stage NOT circuit, followed by three-stage NOT circuit or one-stage NOT circuit. With such arrangement, a temperature detection circuit with no or less manufacturing deviations is completed. By utilization of this circuit, the refresh interval of self-refresh operation of a DRAM at low temperature may be expanded to be a multiple integer longer than a given reference interval to assure self-refresh operation at the optimum refresh interval within a wide range of temperature, and power consumption of the DRAM may be reduced at low temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.