Semiconductor memory apparatus with reduced line widths
US5375095A · kind A · utility
34Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1991 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Jun 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory is formed with two power supply meshes extending throughout a memory array region in which are formed memory cells and sense amplifier circuits, thereby enabling sense amplifier drive circuits to be distributed throughout that memory array region, with each sense amplifier drive circuit being connected to the nearest points on the two supply meshes. A substantially improved value of read access time, or increased total memory capacity, can thereby be achieved by comparison with a DRAM in which the sense amplifier drive circuits are provided only at the periphery of a memory array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.