Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
US5375215A · kind A · utility
51Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1991 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Oct 29, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.