Apparatus and method to test random access memories for a plurality of possible types of faults
US5377148A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 29, 1990 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Nov 29, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a test method of the complexity of 7n to test RAM devices, where n is the number of bits. This method tests all cell stuck-at-1/0 faults, state transition 1-to-0 and 0-to-1 faults, state coupling faults between two cells and data retention faults in random access memories. A standardized testable design memory (STD architecture) is presented which keeps the time required to test a RAM constant irrespective of the memory size. The design is shown through four examples to cover both bit and byte oriented memories. The memory address decoder is implemented in two or more levels. The decoder decoding the most significant addressed is modified by addition of an external control signal line. Memory of the RAM (memory cell array) is partitioned into blocks. The size of these blocks is defined by the last level (least significant address) of the memory address decoder. The design is highly structured and requires a very small amount of extra hardware. The architecture is not only applicable at chip level, but also at the board level. A slight modification allows fault diagnosis to be achieved in the STD architecture. This architecture also permits disconnecti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.