Rochit Rajsuman
29Patents
16h-index
16Co-inventors
74Inventor score
Filing activity: Nov 29, 1990 → Apr 11, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6678645B1 | Method and apparatus for SoC design validation | Physics | 164 | Expired |
| US6249893A | Method and structure for testing embedded cores based system-on-a-chip | Physics | 100 | Expired |
| US5670890A | Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits | Physics | 38 | Expired |
| US6408412B1 | Method and structure for testing embedded analog/mixed-signal cores in system-on-a-chip | Physics | 35 | Expired |
| US6629282B1 | Module based flexible semiconductor test system | Physics | 35 | Expired |
| US6532561B1 | Event based semiconductor test system | Physics | 34 | Expired |
| US6108805A | Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits | Physics | 33 | Expired |
| US6651204B1 | Modular architecture for memory testing on event based test system | Physics | 28 | Expired |
| US5377148A | Apparatus and method to test random access memories for a plurality of possible types of faults | Physics | 28 | Expired |
| US6377065B1 | Glitch detection for semiconductor test system | Physics | 25 | Expired |
| US5644251A | Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits | Physics | 23 | Expired |
| US6249889A | Method and structure for testing embedded memories | Physics | 23 | Expired |
| US6567941B1 | Event based test system storing pin calibration data in non-volatile memory | Physics | 19 | Expired |
| US6249892A | Circuit structure for testing microprocessors and test method thereof | Physics | 19 | Expired |
| US5867036A | Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits | Physics | 17 | Expired |
| US6804620B1 | Calibration method for system performance validation of automatic test equipment | Physics | 17 | Expired |
| US5963566A | Application specific integrated circuit chip and method of testing same | Physics | 16 | Expired |
| US6747447B2 | Locking apparatus and loadboard assembly | Physics | 15 | Expired |
| US6404218B1 | Multiple end of test signal for event based test system | Physics | 14 | Expired |
| US6948105B2 | Method of evaluating core based system-on-a-chip (SoC) and structure of SoC incorporating same | Electricity | 13 | Expired |
| US7089517B2 | Method for design validation of complex IC | Physics | 13 | Expired |
| US7178115B2 | Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing | Electricity | 10 | Expired |
| US7089135B2 | Event based IC test system | Physics | 9 | Expired |
| US6578169B1 | Data failure memory compaction for semiconductor test system | Physics | 8 | Expired |
| US6944808B2 | Method of evaluating core based system-on-a-chip | Physics | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.