JTAG instruction error detection
US5377198A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1991 |
| Grant date | Dec 27, 1994 |
| Priority date | — |
| Expiry date | Nov 27, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318569
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for detecting JTAG errors in which components in a boundary scan path of a JTAG serial test bus connect a single bit bypass register into the scan path rather than the expected register when errors are detected. JTAG instruction signals are shifted into the scan path to determine whether an instruction error was received by a component. Data scanned into the component is prefixed by a header which is monitored by the JTAG control circuitry to detect any instruction errors. The combined data and header are padded by bits preceding the header to be equal to a multiple of a data register contained within the JTAG control circuitry. The least significant bit positions of the header and the padding bits are shifted out of the data register prior to the time that the header or first byte of the header should have been in the data register of the JTAG control circuitry such that the least significant bit of the data register is a 1, if no single error occurred, and is a 0 if a single error occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.