Method for controlling the etching profile of a layer of an integrated circuit
US5378309A · kind A · utility
33Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 5, 1992 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Aug 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention concerns a process for slope etching a layer of an integrated circuit. The layer to be etched is coated with a masking photoresist layer. The process consists of jointly performing a passivation of the etching flank of the layer to be etched and a nonisotropic erosion of the masking photoresist layer, which makes it possible to control the slope of the etching flank of the layer to be etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.