Electrically programmable non-volatile semiconductor memory device and manufacturing method thereof
US5378643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1992 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Dec 31, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
An A-1 transistor type flash EEPROM is disclosed. The memory cell in the EEPROM comprises: a first control gate which is formed, through a first insulating film, on a first channel region formed between a source region and a drain region. A floating gate is formed on the second channel region through a second insulating film and on the first control gate through the first interlayer insulating film. A second control gate is formed on a surface of the floating gate through a second interlayer insulating film. One end of the second control gate and one end of the first control gate are electrically connected to each other through a third control gate, thereby enhancing capacitance between the control gates and the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.