Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas
US5378649A · kind A · utility
224Cited by
5References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1994 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Apr 8, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
Abstract
This inventions provides a method to form metal lines with smaller line pitches than is possible using the conventional photolithographic single coating process. This invention provides for a double photolithographic process where the surface is coated, exposed and developed twice to form two sets of resist patterns. These resist patterns are used to form metal lines over all the buried bit lines. These metal lines provide better masking of the bit lines from the code implants thereby reducing bit line resistance and increasing ROM read speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.