Patent · US Expired

Flash EEPROM cell having gap between floating gate and drain for high hot electron injection efficiency for programming

US5378909A · kind A · utility

30Cited by
4References
5Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 18, 1993
Grant dateJan 3, 1995
Priority date
Expiry dateOct 18, 2013

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10S257/90

Abstract

A flash or block erase electrically erasable programmable read-only memory (EEPROM) cell (10) includes a substrate (12) having a channel region (22), and a source (28) and a drain (32) formed in the substrate (12) on opposite sides of the channel region (22). A first oxide layer (19), a floating gate (20), a second oxide layer (24) and a control gate (26) are formed over the channel region (22). The cell (10) is programmed by hot electron injection from the drain (32) into the floating gate (20), and erased by Fowler-Nordheim tunneling from the floating gate (20) to the source (28). A gap (36) is provided between a sidewall (20a) of the floating gate (20) and the drain (32) to increase the electric field in the drain depletion region. An oxide sidewall spacer (38) is formed on the first oxide layer (19) in the gap (36) which traps electrons. The gap (36) and sidewall spacer (38) increase the hot electron injection efficiency, and enable programming to be accomplished at high speed, with low applied voltages and at high temperatures.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.