Maximizing improvement to fault coverage of system logic of an integrated circuit with embedded memory arrays
US5379303A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 1991 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Jun 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two related methods and apparatus for determining a binary constant to be output from embedded memory arrays into system logic of an integrated circuit when the system logic is being tested, that maximizes improvement to fault coverage of the system logic, are disclosed. The present invention has particular application to digital system testing. The fault coverage of the system logic is improved due to its controllability and observability are indirectly enhanced by the enhanced controllability of the embedded memory arrays. The first related method and apparatus determines the binary constant based on a testability measure selected for the system logic. The second related method and apparatus determines the binary constant based on results from automated test patterns generation for the integrated circuit. Both methods and apparatus provide a constant that is more effective than a randomly assigned binary constant, but without the expensive computations required for a binary constant determined from all possible enumeration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.