System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations
US5379381A · kind A · utility
49Cited by
15References
15Claims
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Key dates
| Filing date | Aug 12, 1991 |
| Grant date | Jan 3, 1995 |
| Priority date | — |
| Expiry date | Aug 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O controller for transferring data between a host processor and one or more I/O units. The controller interleaves processor command transfers (PIO) in the midst of direct memory access (DMA) transfers without repeated data moves. DMA transfers are suspended temporarily during the priority PIO transfer. An interrupt Scanner, for scanning the various I/O units, is also prioritized with respect to DMA and PIO transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.