Three-dimensional multichip package and methods of fabricating
US5380681A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 1994 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Mar 21, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a three-dimensional multi-chip array package wherein master semiconductor substrate is formed having a peripheral inner row of contact pads and a peripheral outer row of terminal pads. A plurality of subordinate semiconductor substrates are formed provided with a peripheral row of contact pads that match the contact pads on the master substrate. Openings are formed through centers of the contact pads that extend through the subordinate substrates. The subordinate substrates are stacked on the master substrate with the openings in alignment over the contact pads. The openings are then filled with a conductive material to interconnect the contact pads on all its substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.