Semiconductor memory device with improved step protection and manufacturing method thereof
US5381030A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1994 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Apr 26, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device according to the present invention includes a memory cell array region in which memory cells are arranged in array form, a first and a second row decoders arranged respectively on both sides of the memory cell array region, and a plurality of metallic wirings which are arranged within the memory cell array region in parallel to row direction, the respective one ends of the wirings are alternately connected to either of the first row decoder or the second row decoder, and the width of the metallic wirings that extend from the first or the second decoder to predetermined locations within the memory cell array region is greater than the width of the metallic wirings that extend beyond the predetermined locations within the memory cell array region. With the above arrangement, the disconnection at the step part can be prevented, and the pattern formation in the step part becomes possible even if the focus is set at the height of the region with a fine pattern because of the increase in the focal depth of the resolution of the wiring pattern due to the widening of the wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.