Lead-on chip semiconductor device having peripheral bond pads
US5381036A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Aug 16, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.