CMOS buffer having output terminal overvoltage-caused latch-up protection
US5381056A · kind A · utility
9Cited by
7References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Sep 15, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS buffer circuit includes a p-channel MOS transistor having a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source. A first n-channel MOS transistor is connected in series with the p-channel MOS transistor and has a source terminal connected to a reference potential and a drain terminal connected to an output terminal. A second n-channel MOS transistor is connected between and in series with the p-channel MOS transistor and the first n-channel MOS transistor. The second n-channel MOS transistor has a gate terminal connected to the pump voltage source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.