FPGA having PFU with programmable output driver inputs
US5381058A · kind A · utility
51Cited by
6References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | May 21, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, a field programmable gate array includes at least one programmable function unit. The programmable function unit has first and second logic circuits, each providing an output, and first and second output drivers, each having an input. The input of each output driver is adapted to be selectively coupled to the output of either of the logic circuits. A programmable interconnection is provided to selectively couple the input of the two output drivers to the output of a selective one of the logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.