Dynamic random access memory having stacked type capacitor and manufacturing method therefor
US5381365A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Jun 30, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.