Per pin circuit test system having N-bit pin interface providing speed improvement with frequency multiplexing
US5381421A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1992 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Mar 5, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31922
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method, and apparatus for accomplishing the method, for controlling an operation of a test pin of a per-pin semiconductor device test system. The method includes the steps of, during a test cycle, generating a plurality of timing signals, providing a test pattern comprised of M-bits, and decoding the M-bits into one of 2.sup.M first multi-bit control words. In accordance with logical states of bits of the first control word, the method selects specified ones of the timing signals and generates a stimulus signal at a test pin in accordance with the selected specified ones of the timing signals. In accordance with an aspect of the invention, the step of providing provides test patterns at a rate of (x) test patterns per second, the step of generating generates test pin stimulus signals at a rate of (y) stimulus signals per second, and wherein (y)=n(x), where (n) is an integer greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.