Interleaved shift register
US5381455A · kind A · utility
10Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Apr 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock signals, each of the plurality of clock signals being incrementally out of phase with one another. Interleaved shift register 20 provides multiple data bits of the data signal to be stored within a single clock period of one of the plurality of clock signals, thus greatly improving the data rate without increasing the storage rate of the plurality of data storage elements 22a-22d.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.