Dynamic flow instruction cache memory organized around trace segments independent of virtual address line
US5381533A · kind A · utility
134Cited by
2References
19Claims
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Key dates
| Filing date | Mar 30, 1994 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Mar 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory addresses. A single access to the cache memory may cross virtual address line boundaries. Branch prediction is integrally incorporated into the cache array permitting the crossing of branch boundaries with a single access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.