Method and apparatus for separate mark and wait instructions for processors having multiple memory ports
US5381536A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 1994 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | May 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus for handling memory hazards in processors having multiple memory ports wherein the operation of marking of the memory requests that may be related to a memory hazard is separated from the operation of waiting for the memory hazard to clear. The separation of the operation of marking of memory hazards from the operation of waiting for memory hazards to clear allows a compiler to schedule other instructions, as well as other memory operations not directed to the memory location involved in the memory hazard sequence, during the time between the operations of marking and waiting for the memory hazard to clear. The waiting period ends once it is clear that the marked memory requests will execute in the order in which they were issued.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.